1. Field of the Invention.
The present invention relates to multi-lane coherent transceivers and, more particularly, to a multi-lane coherent transceiver with synchronized lane reset signals.
2. Description of the Related Art.
A multi-lane coherent transceiver is a transceiver that has a number of outputs where the data to be transmitted is precisely aligned and synchronized across the different outputs. Multi-lane coherent transceivers are commonly used to increase the amount of data that can be transmitted. For example, a four-lane synchronous transceiver can output four times as much data as a transceiver with only a single output.
In operation, a multi-lane coherent transceiver can receive low-speed digital input signals, such as from a Digital Signal Processing (DSP) unit, and then serialize the input signals using a high-speed clock to form a number of high-speed digital signals. The high-speed digital signals drive analog drivers, which output corresponding analog signals.
Multi-lane coherent transceivers commonly utilize a clock generation circuit that includes a phase-lock-loop (PLL) and a frequency divider. The PLL generates the high-speed clock signal, which is fanned out to each of the lanes, while the frequency divider divides down the high-speed clock signal to form a low-speed clock signal, which is also fanned out to each of the lanes.
The order of the serialized high-speed data is determined by a reset signal that gates or enables the frequency divider. The reset signal is generated by a state machine which is controlled by software or firmware, and therefore the reset signal is not synchronous to the high-speed clock signal in each lane.
One issue with multi-lane coherent transceivers is that the reset signal can potentially be asserted during metastable states of the flip-flops in the clock generation or data register circuits. Jitter and skew in either the clock or reset signal can cause different clock startup timing, which translates into different data orders between different lanes.
FIGS. 1A-1E show timing diagrams that illustrate an example of a potential timing issue with prior-art multi-lane coherent transceivers. FIG. 1A shows a reset signal RST, FIG. 1B shows a lane 0 clock signal CLKL0,
FIG. 1C shows a lane 1 clock signal CLKL1, FIG. 1D shows a first sampled signal FSS, and FIG. 1E shows a second sampled signal SSS.
As shown in the FIGS. 1A-1E example, at time to, the reset signal RST is low when the lane 1 clock signal CLKL1 changes state. At time t1, the reset signal RST is high when the lane 0 clock signal CLKL0 changes state. This slight difference in timing causes the second sampled signal SSS for lane 1 to change state nearly a full clock cycle after the first sampled signal FSS for lane 0 changed state. This delay or skew, in turn, can cause different clock startup timing, which translates into different data orders between different lanes.
Thus, there is a need for a multi-lane coherent transceiver with synchronized lane reset signals that reduces these potential timing issues.